AN124 external synchronization for the ne5561/5568 1988 dec integrated circuits www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors application note AN124 external synchronization for the ne5561/5568 2 1988 dec synchronization of the 5561 can be accomplished by forcing the timing pin (pin 5) above the 5.6v sawtooth limit comparator for a short time. +5.6v +1.1v timing sawtooth +1v (typ) external sync sl00788 figure 1. this can be accomplished with a simple diode-coupled narrow pulse source with fairly low source impedance: ne5561/ 5568 2 5 8.4v in914 100pf sync 1v 0 r t c t sl00789 figure 2. a drawback to this approach is that when the 5.6v threshold is reached, a discharge transistor is turned on to quickly pull the timing capacitor to ground and will also attempt to pull the pulse generator to ground. this condition can be avoided by keeping the pulse width very narrow (0.1 m s) or by placing a differentiator network between the pulse generator and the diode. the dif ferentiator will now produce a positive-going spike with the positive edge of the sync pulse, resetting the sawtooth without passing too much current through the discharge transistor . the negative spike produced by the falling edge of the clock will be blocked by the diode and will have no ef fect on the sawtooth ramp. a narrow sync pulse is no longer necessary while a sharp-edged pulse is. the value of c d should be sufficient to ensure that a 10v pulse will drive the capacitor, c t , high enough to trip the 5.6v comparator according to: c t d v ct =c d ( d v ct -v d ) this relates the magnitude of the spike to the size of the pulse. also assume r d c d <1 m s. the free-running frequency of the slaved 5561 should be slightly lower than the sync frequency for proper operation. www.datasheet.co.kr datasheet pdf - http://www..net/
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